In a continuous-time world, establishing a common time base at physically separated locations presents some serious challenges. Typical systems use independent time bases, frequently derived from crystal oscillators. Although crystal oscillators provide extremely accurate timing references at low cost, “extremely accurate” is not adequate to maintain the integrity of discrete-time data. Timing references often have to be identical, at least in the sense of long term averages. In other words, systems must be synchronized. Underlying most synchronization techniques is the phase-locked loop (PLL).
The discrete-time PLL, described in relation to the prior art Figures hereinafter, can be used to synchronize an output signal to an input signal. If there is more than one set of input/output signals to be synchronized, then two discrete time PLLs are necessary. The number of resources or discrete-time PLLs required for implementation scales linearly with the number of input/output pairs of signals.
Typically, discrete-time PLLs are implemented in digital signal processing (DSP) chips, application specific integrated circuits (ASICs), and/or field programmable gate arrays (FPGAs). All such hardware, while experiencing continuous growth in both speed and available on-chip resources, faces limitations in the number of basic building blocks available for discrete-time PLL use including registers (memory), multipliers, accumulators, and adders/subtractors. In real time systems where numerous signals are to be synchronized, resources are quickly diminished as new hardware is allocated to provide a discrete-time PLL to each signal path. It is thus significantly advantageous to develop a means to share on-chip hardware resources across multiple input/output signal pairs.